Wafer level packaging (WLP) refers to the technology of packaging semiconductor chips at the wafer level, instead of the traditional process of packaging semiconductor chips one at a time. WLP is a chip-scale packaging technology, since the resulting package is substantially the same size as the chip. WLP consists of extending wafer fabrication processes to provide device connections and protection.
Wafer level ball grid array (WLB) packaging is one type of WLP. Typically, a semiconductor device fabricated using WLB technology includes a semiconductor chip or die electrically coupled to an array of solder balls or bumps via a redistribution layer (RDL). The solder balls or bumps are situated within the footprint of the semiconductor chip. A semiconductor device fabricated using WLB technology is coupled to a printed circuit board (PCB) by soldering the solder balls to the PCB.
Embedded wafer level ball grid array (eWLB) packaging expands on WLB packaging by providing the ability to add surface area to the footprint of the semiconductor chip. In eWLB packaging, a mold material or compound encapsulates the semiconductor chip opposite the RDL and the array of solder balls. This mold material expands the surface area that can be used for solder balls or bumps. A semiconductor device fabricated using eWLB technology is coupled to a PCB by soldering the solder balls to the PCB.
Typically, each of the semiconductor devices fabricated via either WLB technology or eWLB technology includes multiple layers applied via thin-film technologies. One layer is an insulating layer that pacifies the wafer. Another layer is a RDL that routes chip inputs and outputs to solder landing pads, and a third layer is a solder stop layer that stops solder flow and protects the RDL from oxidation and corrosion. Usually, the solder stop layer is a certain thickness to stop solder flow and prevent cracking of the solder stop layer.
Increasing the thickness of the insulating layer improves the operation of the integrated circuit on the semiconductor chip. However, increasing the thickness of the multiple layers increases stress on the semiconductor chip and warping of the semiconductor device. Increased warping of the semiconductor device may prevent pick and place tools from operating properly.
For these and other reasons, there is a need for the present invention.